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| PAS5101CS Specification PAS5101CS CMOS 1.3MEGA DIGITAL IMAGE SESNSOR General Description The PAS5101CS is a highly integrated CMOS active-pixel image sensor that has resolution of 1280( H ) x 1024 ( V ). To have an excellent image quality, the PAS5101CS output 10-bits RGB raw data though a parallel data bus. It is available in 24-pin CSP. The PAS5101CS can be programmed to set the exposure time for different luminance condition via I2CTM serial control bus. By programming the internal register sets, it performs on-chip frame rate adjustment, offset correction DAC, programmable gain control, 10-bits ADC, 10-bits output companding, interpolated subsampling and defect compensation. w w w Features . D a t a S h e e t 4 U . c o m Key Specification Supply Voltage Resolution Array Diagonal Pixel Size Max. Frame Rate Max. System Clock Max. Pixel Clock Color Filter Exposure Time Scan Mode Sensitivity S/N Ratio Chief Ray Angle Package Type 2.5v ~ 3.3v 1280 ( H ) x 1024 ( V ) 5.9mm ( ~1/3" Optic ) 3.6m x 3.6m ~15 fps @ 1.3Mega Up to 48MHz Up to 24MHz RGB Bayer Pattern ~ Frame time to Line time Progressive TBD TBD 20 ~ 24 24-pin CSP 1.3Mega resolution, ~1/3" Lens. Bayer RGB color filter array. 10-bits parallel RGB raw data output. On-Chip 10-bits pipeline A/D converter. On-Chip programmable gain amplifier 4-bits color gain amplifier. 4-bits global gain amplifier. Digital gain stage. Continuous variable frame time. Continuous variable exposure time. I2CTM interface. 20mA power dissipation ( 15fps / 2.5v ). < 10uA low power-down dissipation. Window-of-Interest (WOI). Sub-sampling. Defect compensation. Lens shading compensation. Pin-to-pin compatible to OV9640. All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. 1 PixArt Imaging Inc. E-mail: fae_service@pixart.com.tw v1.0 2005/4/27 PAS5101CS Specification 1. Pin Assignment www..com Figure 1.1 Shows the PAS5101CS pin diagram Pin No. E4 D4 E5 D5 C5 B5 A5 B4 A4 B3 A3 B2 A2 B1 A1 C1 D1 E1 D2 E2 C4 Name VSSA VDDA PWDN VREF VDDD VSYNC HSYNC PXCLK VDDQ SYSCLK RESET VSSD PX9 PX8 PX7 PX6 PX5 PX4 PX3 PX2 PX1 Type GND PWR IN IN PWR OUT OUT OUT PWR IN IN GND OUT OUT OUT OUT OUT OUT OUT OUT OUT Analog ground. Analog power, 2.5V Power Down (chip power down if high ). Internal voltage reference. Nc, Internal Regulator 1.8V. Vertical synchronization signal. Horizontal synchronization signal. Pixel clock output. Sensor VDD, 2.5V ~ 3.3V. System clock input. Resets all registers to their default values ( chip reset if high .) Digital ground. Digital data out. Digital data out. Digital data out. Digital data out. Digital data out. Digital data out. Digital data out. Digital data out. Digital data out. 2 Description All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. PixArt Imaging Inc. E-mail: fae_service@pixart.com.tw v1.0 2005/4/27 PAS5101CS Specification C2 D3 E3 PX0 SCL SDA OUT IN I/O Digital data out. I2C clock. I2C data. Internal pull high resister is 10K. 2. Sensor Array Format & Output Timing 2.1. Physical Sensor Array Format www..com Figure 2.1 Physical Sensor Array Format 2.2. Output Timing 1.3Mega mode ( 1288 x 1032 ) pixel readout: H_Start[9:0] = 0, LPF[7:0] = 1035, V_Start[8:0] = 0, Nov_Size_By4[7:0] = 63, H_Size[9:0] = 1287, V_Size[8:0]= 1035, Figure 2.2 Inter-line timing All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. 3 PixArt Imaging Inc. E-mail: fae_service@pixart.com.tw v1.0 2005/4/27 PAS5101CS Specification Figure 2.3 Inter-frame timing www..com Figure 2.4 Inter-frame timing @ Dark masked All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. 4 PixArt Imaging Inc. E-mail: fae_service@pixart.com.tw v1.0 2005/4/27 PAS5101CS Specification 3. Block Diagram & Function Description 3.1. Block Diagram www..com Figure 3.1 Shows the PAS5101CS sensor block diagram The PAS5101CS is a 1/3" CMOS imaging sensor with 1280 ( H ) x 1024 ( V ) physical pixels. The active region of sensor array is 1288 ( H ) x 1032 ( V ) as shown in Figure 3.1. The sensor array is cover with Bayer pattern color filters and -lens. The first pixel location ( 0,0 ) is programmable in 2 direction ( X and Y ) and the default value is at the left-down side of sensor array. After a programmable exposure time, the image is sampled first with CDS ( Correlated Double Sampling ) block to improve S/N ration and reduce fixed pattern noise. Three analog gain stages are implemented before signal transferred by the 10-bits A/D converter. The front gain stage ( FG ) can be programmed to fit the saturation level of sensor to the full-range input of ADC. The programmable color gain stage ( CG ) is used to balance the luminance response difference between B/G/R. The global gain stage ( GG ) is programmed to adapt the gain to the image luminance. The fine gained signal will be digitized by the on-chip 10-bits A/D converter. After the image data has been digitized, further alteration to the signal can be applied before the data is output. 3.2. Defect Compensation The defect compensation block can detect the possible defect pixel and replace it with average output of like-colored pixels on either side of defective pixel. There is no limitation in the capability of defect number. This function is also Enable / Disable by user. 3.3. Companding Curves The companding function is used to simulate the gamma curve and do non-linear transformation before the data is output. There are 4 curves selected by setting register Compand_Sel as shown in Figure 3.2 and this function is also Enable / Disable by user. All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. 5 PixArt Imaging Inc. E-mail: fae_service@pixart.com.tw v1.0 2005/4/27 PAS5101CS Specification www..com Figure 3.2 Companding curves program by Compand_EnH and Compand_Sel 3.4. Power Down Mode The PAS5101CS can be power down by setting register "SW_PwrDn" or by enable PWDN pin. PAS5101CS supports two power down modes : Software Power Down : Set register "SW_PwrDn" = 0x01 to power down all the internal block except I2CTM. Hardware Power Down : Pull PWDN pin to high to power down the chip. The chip will go into standby mode. 3.5. Reset Mode The PAS5101CS can be reset by setting "SW_Reset" or by enable Reset pin. PAS5101CS supports two reset modes : Software Reset : Set register "SW_Reset" = 0x01 to reset all the I2CTM registers. It's only reset the register value not reset full chip. HardwareReset : Pull Reset pin to high to reset the full chip. 3.6. Window-of-Interest ( WOI ) Users are allowed to define window size as well as window location in PAS5101CS. The location of window can be anywhere in the pixel array. Window size and window location is defined by register "H_Start", "V_Start", "V_Size" and "H_Size"; The "H_Start" defines the starting column while "V_Start" defines the starting rom of the window; The "H_Size" define the column width of the window and "V_Size" defines the row depth of the window. All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. 6 PixArt Imaging Inc. E-mail: fae_service@pixart.com.tw v1.0 2005/4/27 PAS5101CS Specification www..com Figure 3.3 3.7.1. Output timing of WOI Hardware windowing VGA ( 640x480 ) pixels readout ( With 4 dark lines ): H_Start[9:0] = 0, LPF[7:0] = 483, V_Start[8:0] = 0, Nov_Size_By4[7:0] = 63, H_Size[9:0] = 639, V_Size[8:0]= 483, Figure 3.4 Inter-line timing of W.O.I Figure 3.5 Inter-frame timing of W.O.I All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. 7 PixArt Imaging Inc. E-mail: fae_service@pixart.com.tw v1.0 2005/4/27 PAS5101CS Specification 3.7. Sub-Sampling PAS5101CS can be programmed to output image in VGA QVGA and QQVGA size. In the VGA subsampling mode, both vertical and horizontal pixels are sub-sampling at 1/2; In QVGA sub-sampling mode, both vertical and horizontal pixels are sub-sampling at 1/4; While in QQVGA sub-sampling mode, subsampling at 1/8. By programming Skip_Analog and Skip_Digital, The maximum sub-sampling rate is 1/32 ( Skip_Analog + Skip_Digital ). 3.7.1. Skip_Analog Sub-sampling ( Skip_Analog ) to VGA ( 640x480 ) pixels readout ( With 4 dark lines ): H_Start[9:0] = 0, www..com V_Start[8:0] = 0, H_Size[9:0] = 1287, V_Size[8:0]= 1035, LPF[7:0] = 519, Nov_Size_By4[7:0] = 63, Skip_Analog = 1 ( sub-sampling 1/2 ) Figure 3.6 Valid pixel = ( H_Size + 1 ) / Skip_Analog = 1288 / 2 = 644 Valid line = (((( V_Siez + 1 ) - 4 ) / Skip_Analog ) + 4) = (((( 1035 + 1 ) - 4 ) / 2 ) + 4 ) = 520 Figure 3.7 Inter-line timing of W.O.I All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. 8 PixArt Imaging Inc. E-mail: fae_service@pixart.com.tw v1.0 2005/4/27 PAS5101CS Specification Figure 3.8 Inter-frame timing of W.O.I 3.7.2. www..comSkip_Digital Sub-sampling ( Skip_Digital ) to VGA ( 640x480 ) pixels readout ( With 4 dark lines ): H_Start[9:0] = 0, LPF[7:0] = 1036, V_Start[8:0] = 0, H_Size[9:0] = 1287, V_Size[8:0]= 1035, Nov_Size_By4[7:0] = 63, Skip_Digital = 1 Valid pixel = ( H_Size + 1 ) / Skip_Digital = 1288 / 2 = 644 Valid line = ( V_Siez + 1 ) / Skip_Digital = ( 1035 + 1 ) / 2 = 518 Figure 3.9 Inter-line timing Figure 3.10 Inter-frame timing All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. 9 PixArt Imaging Inc. E-mail: fae_service@pixart.com.tw v1.0 2005/4/27 PAS5101CS Specification 4. I2CTM Bus PAS5101CS supports I2C bus transfer protocol and is acting as slave device. The 7 bits unique slave address is "1000000" and supports receiving / transmitting speed up to 400KHz. 4.1. I2C Bus Overview Only two wires SDA ( serial data ) and SCL ( serial clock ) carry information between the devices connected to the I2C bus. Normally both SDA and SCL lines are open collector structure and pull high by external pull-up resistors. Only the master can initiates a transfer ( start ), generates clock signals, and terminates a transfer ( stop ). www..com Start and stop condition : A high to low transition of the SDA line while SCA is high defines a start condition. A low to high transition of the SDA line while SCA is high defines a stop condition. Please refer to Figure 4.1. Valid data : The data on the SDA line must be stable during the high period of the SCA clock. Within each byte, MSB is always transferred first. Read / Write control bit is the LSB of the first byte. Please refer to Figure 4.2. Both the master and slave can transmit and receive data from the bus. Acknowledge : The receiving device should pull down the SDA line during high period of the SCL clock line when a complete byte was transferred by transmitter. In the case of a master received data from a slave, the master does not generate an acknowledgment on the last byte to indicate the end of a master read cycle. Figure 4.1 Start and Stop conditions Figure 4.2 Valid Data All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. 10 PixArt Imaging Inc. E-mail: fae_service@pixart.com.tw v1.0 2005/4/27 PAS5101CS Specification 4.2. Data Transfer Format 4.2.1. Master transmits data to salve ( write cycle ) S : Start. A : Acknowledge by salve. P : Stop. RW : The LSB of 1ST byte to decide whether current cycle is read or write cycle. RW = 1 - Read cycle, RW = 0 - Write cycle. SUBADDRESS : The address values of PAS5101CS internal control registers. ( Please refer to PAS5101CS register description ) www..com During write cycle, the master generates start condition and then places the 1st byte data that are combined slave address ( 7 bits ) with a read / write control bit to SDA line. After slave ( PAS5101CS ) issues acknowledgment, the master places 2nd byte ( Sub Address ) data on SDA line. Again follow the PAS5101CS acknowledgment, the master places the 8 bits data on SDA line and transmit to PAS5101CS control register ( address was assigned by 2nd byte ). After PAS5101CS issue acknowledgment, the master can generate a stop condition to end of this write cycle. In the condition of multi-byte write, the PAS5101CS sub-address is automatically increment after each DATA byte transferred. The data and A cycles is repeat until last byte write. Every control registers value inside PAS5101CS can be programming via this way. 4.2.2. Slave transmits data to master ( read cycle ) The sub-address was taken from previous write cycle. The sub-address is automatically increment after each byte read. Am : Acknowledge by master. Note there is no acknowledgment from master after last byte read. All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. 11 PixArt Imaging Inc. E-mail: fae_service@pixart.com.tw v1.0 2005/4/27 PAS5101CS Specification During read cycle, the master generates start condition and then place the 1st byte data that are combined slave address ( 7 bits ) with a read / write control bit to SDA line. After issue acknowledgment, 8 bits DATA was also placed on SDA line by PAS5101CS. The 8 bits data was read from PAS5101CS internal control register that address was assigned by previous write cycle. Follow the master acknowledgment, the PAS5101CS place the next 8 bits data ( address is increment automatically ) on SDA line and then transmit to master serially. The DATA and Am cycles is repeat until the last byte read. After last byte read, Am is no longer generated by master but instead by keep SDA line high. The slave ( PAS5101CS ) must releases SDA line to master to generate STOP condition. www..com 4.3. I2CTM Bus Timing 4.4. I2CTM Bus Timing Specification Parameter SCL clock frequency. Hold time ( repeated ) Start condition. After this period, the first clock pulse is generated. Low period of the SCL clock. High period of the SCL clock. Set-up time for a repeated START condition. Symbol fscl tHD:STA tLOW tHIGH tSU;STA Standard Mode Min. 10 4.0 4.7 0.75 4.7 Max 400 Unit KHz s s s s 12 All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. PixArt Imaging Inc. E-mail: fae_service@pixart.com.tw v1.0 2005/4/27 PAS5101CS Specification Data hold time. For I2C-bus device. Data set-up time. Rise time of both SDA and SCL signals. Fall time of both SDA and SCL signals. Set-up time for STOP condition. Bus free time between a STOP and START. Capacitive load for each bus line. www..com Noise margin tHD;DAT tSU;DAT tr tf tSU;STO tBUF Cb VnL VnH 0 250 30 30 4.0 4.7 1 0.1 VDD 3.45 N.D. N.D. 15 - s ns ns ( notel ) ns ( notel ) s s pF V V at LOW level for each connected device. ( Including hysteresis ) Noise margin at HIGH level for each connected device. ( including hysteresis ) 0.2 VDD Note : It depends on the "high" period time of SCL. All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. 13 PixArt Imaging Inc. E-mail: fae_service@pixart.com.tw v1.0 2005/4/27 PAS5101CS Specification 5. Specifications Absolute Maximum Ratings Ambient Storage Temperature VDDD Supply Voltage ( with respect to ground ) VDDA VDDQ -40 ~ +125 3V 3V 4V -0.3V to VDDQ + 1V +230 2000V www..comAll Input / Output Voltage ( with respect to ground ) Lead temperature, Surface-mount process ESD rating, Human Body model DC Electrical Characteristics ( Ta = 0 ~ 70 ) Symbol VDDA VDDD VDDQ IDD IPWDN Parameter Type : POWER DC supply voltage - Analog DC supply voltage - Digital DC supply voltage - I/O Operating Current ( ~ 15fps / 2.5v ) Power Down Current Type : IN & I/O Reset and System Clock VIH VIL CIN Input Voltage HIGH Input Voltage LOW Input Capacitor 0.7 x VDDQ 0.3 x VDDQ 10 V V pF 2.4 20 10 2.4 2.5 1.8 3.3 2.6 V V V mA A Min. Typ. Max. Unit Type : OUT & I/O for PX 0 : 7, PXCLK, H/VSYNC & SDA, load 10pF, 1.2K, 2.5V VOH VOL Output Voltage HIGH Output Voltage LOW 0.9 x VDDQ 0.1 x VDDQ V V All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. 14 PixArt Imaging Inc. E-mail: fae_service@pixart.com.tw v1.0 2005/4/27 PAS5101CS Specification AC Operating Condition Symbol Sysclk Pxclk Parameter Master clock frequency Pixel clock output frequency Min. Typ. Max. 48 24 Unit MHz MHz Sensor Characteristics Parameter www..com Typ. TBD TBD TBD Operation Stable Image -10 ~ +70 0 ~ +50 Unit V/Lux-sec dB dB Sensitivity Signal to Noise Ratio Dynamic Range Temperature Range All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. 15 PixArt Imaging Inc. E-mail: fae_service@pixart.com.tw v1.0 2005/4/27 6. AGND JP1 www..com PXCLK SYSCLK PWDN RESET VDDA B4 B3 E5 A3 D4 E4 PXCLK PWDN SCL DGND C5 B2 DGND D5 C2 A2 0.1uF AGND B1 PX8 PX9 VDDD VSSD VREF PX9 PX8 PX5 PX6 PX7 SYSCLK SCL VDDQ D3 RESET VDDA VSSA A4 VDDQ SDA E3 SDA VSY NC B5 VSY NC PAS5101CS HSY NC A5 HSY NC PX0 C2 PX0 VDDQ PX9 SY SCLK PX8 DGND PX7 PXCLK PX6 PX2 PX5 PX3 PX4 PX1 PX0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 AGND AGND SDA VDDA SCL RESET VSY NC PWDN HSY NC CONN FLEX 24/SM 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 PX2 PX3 E2 D2 E1 PX4 D1 C1 PX2 PX3 PX4 PX5 PX6 All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. PX7 A1 E-mail: fae_service@pixart.com.tw C1 0.1uF AGND PixArt Imaging Inc. Reference Circuit Schematic U1 PX1 C4 PX1 Notes: VDDQ is 2.5V ~ 3.3V sensor IO power. VDDA is 2.5V sensor analog power. C1 should close to sensor VDDA and AGND. C2 should close to sensor VREF and AGND. 16 PAS5101CS Specification v1.0 2005/4/27 PAS5101CS Specification 7. Package Information D C B A E www..com 1107 800 800 415 center of sensor 5 Top view (Bumps down) 5585 3 101.81 4 Center of the package (It's not same as center of BGA) 1 5 1193 C Bottom view (Bumps up) 2 4 800 D AB 3 281.4 center of BGA 2894 1 D C B A 2426 E 640 5445 Side view 160 2 All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. 17 PixArt Imaging Inc. E-mail: fae_service@pixart.com.tw v1.0 2005/4/27 PAS5101CS Specification 8. Reflow Profile for Non Lead-Free www..com All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. 18 PixArt Imaging Inc. E-mail: fae_service@pixart.com.tw v1.0 2005/4/27 PAS5101CS Specification 9. Lens & Holder 9.1. LarGan 40-900L 9.2. LarGan 40-519C 9.3. MaxEmil SS-4828GA 9.4. PEH-0116-03AA www..com All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission. 19 PixArt Imaging Inc. E-mail: fae_service@pixart.com.tw v1.0 2005/4/27 |
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